1. Field of the Invention
This invention relates to capacitor averaging converters and more particularly, though not exclusively, to capacitor averaging pipeline analog-to-digital converters.
2. Description of Related Art
In past 20 years, highly accurate data conversion using pipeline architecture has been studied and developed. Both analog compensation and digital calibration schemes were successfully proposed to achieve high accuracy—up to 15 b resolution. The main effort regarding analog compensation schemes has been to compensate the capacitor mismatch of switched-capacitor pipeline stages, which is a limitation on the high resolution pipeline analog to digital converter (ADC) designs.
One technique used a dedicated opamp-based switched-capacitor stage to perform charge averaging in a separate averaging phase. Unfortunately, this first technique had high power consumption, and its operating speed was limited to 20 Msps. In part, the first of these problems was due to the active averaging technique that relied on an opamp-based feedback network, which consumes large quantities of power. Also, this first technique must operate in at least three clocks phases for residual signal generation. As a result, large currents were drained, and the data conversion rate was significantly slower.
As shown in FIGS. 1 and 2, another technique proposed was a passive capacitor averaging scheme to cut down power dissipation. This technique twice samples the residual signal into two nominally identical capacitors of the next pipeline stages. The charges on the two capacitors are redistributed in an averaging manner among the shorted capacitors in the next clock phase. This is done by an opamp-based switched capacitor circuit, completing the averaging process. The switched capacitor circuit was also used as residual amplifier. As a result, no dedicated averaging stage is required for the structure, thus saving power. Also, only a few switches were added to control the double sampling of residual signals.
Still referring to FIGS. 1 and 2, four clock phases are required to output one residual signal from each pipeline stage. For pipeline stage-(i), during sampling phase Φ1, switches S1 and S2 are closed to acquire an input signal. Switches S3 & S4 are also closed for bottom-plate sampling. One additional sampling phase Φ2 (or comparison phase) may be used to perform sub-ADC data conversion within each pipeline stage. Φ1 & Φ2 schematics are not shown). This is preferable but not mandatory as other comparison techniques can be used to eliminate the need for the additional phase Φ2. In these two clock phases, the associated opamp is idle.
During amplification phase Φ3, the sampling switches S1, S2, S3 and S4 are open and isolate the switched capacitor circuit from an input signal. At almost the same time, switches S0 & S5 are closed and a loop is formed around the opamp for residual amplification with gain of (1+C1S1/C1S2). The stage (i+1) is sampling the residual signal from stage (i) into a capacitor C1S2. In the last phase Φ4, the capacitors C1S1 and C2S1 are swapped to provide a slightly different gain of (1+C2S1/C1S1). This will be different to the gain (1+C1S1/C1S2) because of inherent capacitor mismatch between C1S1 and C2S2. The stage (i+1) is again sampling the signal into another sampling capacitor C2S2. In this way, the charges on the two capacitors can be redistributed later by a switched capacitor circuit and the resultant compensated residual signal can be obtained. This will be subject only to the second-order error, which is very small and is normally of the order of about 10−6. Accordingly, the averaging process needs at least three clock phases to operate properly, thereby slowing the operation. Therefore, there is a need for an improved capacitor averaging converter.